Using Xtext to build billion transistor chips and IoT devices
Building a modern billion transistor System-on-a-Chip (SoC) is a complex task requiring the integration of hundreds of customizable IP components and connections between them. The software to create these complex chips consists of various code-generators, performance simulators, logic synthesis tools, performance databases and place-and-route tools. Each tool typically uses its own domain specific languages to describe the input and outputs. Abstraction and good user interface are essential to successfully transform an architectural concept in to a power optimized and performance-tuned chip.
Building a software tool to efficiently configure and automate the design of an SoC is a non-trivial task. Having used XML as the intermediate persistence format; it was found it to be difficult to read and hard to bridge to legacy formats. We found that Xtext and EMF worked well to quickly glue these hardware tools together. Through its facility to specify a domain specific language that closely matched the meta-data of our existing tools, we were able use it to rapidly build a tool to handle the integration of components for large SoC designs consisting of a graphical editor, scriptable interfaces and intelligent text-based entry.
This presentation will cover:
- The lessons and challenges we encountered whilst using Xtext to specify the domain specific language in our flow
- How we used code-generators + Xbase to allow reuse of our existing Python-based validation error checks
- How we used Xtext + Xtend to build code generators and the design patterns used for providing extensible elements of our domain specific language
- The challenges to providing synchronization between various input methods: a Tcl interpreter, a graphical editor and text editor
- Our run-time validation and error checking strategy
- How we used Xpect to test our data-model utilities as well as the correctness of our parser